1. Field of the Invention
The present invention relates generally to the field of semiconductor fabrication and more particularly to methods and apparatuses for forming conductive materials with planarized surfaces within features defined in a substrate, the features having widely different dimensions.
2. Description of the Prior Art
FIG. 1 provides a cross-section of a partially fabricated semiconductor device 100 including a substrate 102 and a conductive layer 104. The substrate 102 is typically a dielectric material and can include trenches of various dimensions such as wide trench 106 and narrow trenches 108. In addition to trenches, the substrate 102 can include other similar features of various dimensions such as vias (not shown). Such features in the substrate 102 are commonly fabricated through well known photolithography processes. The conductive layer 104 is typically a highly conductive metal such as copper (Cu). After further processing, the conductive layer 104 is removed down to the level of the top surface of the substrate 102 such that the conductive material remaining in the trenches 106, 108 and other similar features are electrically separated by the substrate 102 in the finished semiconductor device.
The conductive layer 104 is commonly formed through electroplating with an electroplating solution that contains the metal to be plated. Electroplating is desirable because it is a rapid method for depositing a metal on a surface. One of the drawbacks of electroplating, however, is that voids frequently form in the more narrow features, such as trenches 108, and such voids can cause failures in the finished semiconductor device. Certain additives when added to the electroplating solution can promote rapid filling of the narrow features and prevent void formation, however, these same additives tend to retard the deposition rate in generally fiat areas such as the surfaces between trenches 106, 108 and along the bottom of the wide trench 106.
Accordingly, by the time the conductive layer 104 completely fills the larger features, such as wide trench 106, a substantial thickness, or overburden 110, covers the remainder of the substrate 102. Further, since the additives to the electroplating solution promote rapid filling of the narrow features while retarding it in generally flat areas, an area of superfill 112 can also develop above the level of the top of the overburden 110 over narrow features, as shown in FIG. 1. It will be appreciated that to remove the conductive layer 104 down to the level of the top surface of the substrate 102 requires removing three different thicknesses of material. Unfortunately, the planarization techniques known in the art are poorly suited to such a task, and generally cause dishing 200 over larger features, such as shown over large trench 106 in FIG. 2.
One solution is to electroplate further than is shown in FIG. 1 such that the thickness of the overburden 110 is greater over the entire substrate 102. If carried far enough, the thickness of the overburden 110 tends to even out over the entire substrate 102. The overburden 110 can then be uniformly planarized down to the level of the top surface of the substrate 102. This solution, however, wastes material and is time consuming.
Therefore, what is desired is a method of forming a conductive layer 104 with an overburden 110 that has an essentially planar surface.